I. Field
The present invention relates generally to circuits, and more specifically to a power headswitch.
II. Background
Integrated circuit (IC) fabrication technology continually improves and, as a result, the size of transistors continues to shrink. This enables more transistors and more complicated circuits to be fabricated on an IC die or, alternatively, a smaller die to be used for a given circuit. Smaller transistor size also supports faster operating speed and provides other benefits.
For complementary metal oxide semiconductor (CMOS) technology, which is widely used for digital circuits and some analog circuits, a major issue with shrinking transistor size is standby power. A smaller transistor geometry results in higher electric field (E-field), which stresses a transistor and causes oxide breakdown. To decrease the E-field, a lower power supply voltage is often used for smaller geometry transistors. Unfortunately, the lower power supply voltage also increases the delay of the transistors, which is undesirable for high-speed circuits. To improve the delay, the threshold voltage of the transistors is reduced. However, the lower threshold voltage and smaller transistor geometry result in higher leakage current (or standby current), which is the current passing through a transistor when it is turned off.
Leakage current becomes more problematic as CMOS technology scales smaller. It can be shown that leakage current increases at a high rate with respect to the decrease in transistor size. To illustrate the point, a microprocessor implemented in 0.13 μm (micrometer) CMOS technology may dissipate tens of micro-amps to one milli-amp in standby current when it is powered down. In contrast, it has been estimated that with current technology trends the same microprocessor implemented in 30 nm (nanometer) CMOS technology may dissipate as much as one Ampere of standby current when powered down, which is a thousand or more times greater than the standby current for 0.13 μm CMOS technology. (0.13 μm and 30 nm refer to the “feature” or device length, which is the effective length of a transistor implemented by the CMOS technology.) Leakage current consumes power and reduces standby time for a portable device (e.g., a cellular phone) that uses battery power.
One method of combating high leakage current and reducing standby power consumption in large digital VLSI (very large scale integration) designs is to cut off the power supply to a digital circuit when it is turned off. The power supply may be cut off with either a headswitch or a footswitch. A headswitch is a switch placed between the power supply and the digital circuit. A footswitch is a switch placed between the digital circuit and circuit ground.
A headswitch is conventionally implemented with a P-channel field effect transistor (P-FET) device, which is also referred to as a P-channel transistor. The P-FET device is designed with a sufficiently large size (i.e., the width of the device is sufficiently wide) so that the ON resistance is small and the voltage drop across the device is reduced when the device is turned on. This ensures that power dissipation by the P-FET device is within a desired limit when the device is turned on. However, the large P-FET device size also results in high leakage current when the device is turned off, which is undesirable. Moreover, other issues are encountered when the P-FET device is used as a headswitch, as described below.
There is therefore a need in the art for a headswitch with improved performance over the conventional P-FET headswitch.